non-maskable interrupt

non-maskable interrupt
A hardware-level interrupt that cannot be masked by software, such as a memory parity error.

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  • Non-maskable interrupt — A non maskable interrupt (NMI) is a computer processor interrupt that cannot be ignored by standard interrupt masking techniques in the system. It is typically used to signal attention for non recoverable hardware errors. (Some NMIs may be masked …   Wikipedia

  • Interrupt — This article is about computer interrupts. For the study of the effect of disruptions on job performance, see Interruption science. In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in… …   Wikipedia

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  • Interrupt handler — An interrupt handler, also known as an interrupt service routine (ISR), is a callback subroutine in an operating system or device driver whose execution is triggered by the reception of an interrupt. Interrupt handlers have a multitude of… …   Wikipedia

  • Interrupt Request — Die Artikel Interrupt und Unterbrechungsanforderung überschneiden sich thematisch. Hilf mit, die Artikel besser voneinander abzugrenzen oder zu vereinigen. Beteilige dich dazu an der Diskussion über diese Überschneidungen. Bitte entferne diesen… …   Deutsch Wikipedia

  • Interrupt vector — An interrupt vector is the memory address of an interrupt handler, or an index into an array called an interrupt vector table or dispatch table . Interrupt vector tables contain the memory addresses of interrupt handlers. When an interrupt is… …   Wikipedia

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  • Advanced Programmable Interrupt Controller — In computing, an Advanced Programmable Interrupt Controller (APIC) is a more complex Programmable Interrupt Controller (PIC) than Intel s original types such as the 8259A. APIC devices permit more complex priority models, and Advanced IRQ… …   Wikipedia

  • Programmable Interrupt Controller — A Programmable Interrupt Controller (PIC) is a device which allows priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in the order of their relative priority.… …   Wikipedia

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